TSMC 3DFabric advanced packaging - Taiwan Semiconductor bets on chip stacking at scale
Veröffentlicht: 11.07.2026 um 16:34 Uhr, Redaktion AD HOC NEWS, Redaktionelle Verantwortung: Rafael Müller (Chefredaktion)
TSMC 3DFabric advanced packaging sounds almost quiet in the cleanroom, only the soft hiss of gas and the rhythmic clack of handlers feeding wafers into tools, but this is where Taiwan Semiconductor's most complex chip stacks come together on glassy interposers.
How 3DFabric pulls chips together
3DFabric is TSMC's umbrella brand for its advanced packaging and 3D stack technologies, combining both front-end and back-end process know-how into one platform for system-level integration. It covers several families such as CoWoS, InFO, SoIC and system-on-wafer solutions.
Under this brand, TSMC connects logic dies, high-bandwidth memory (HBM) stacks and other chiplets side by side or vertically to build dense packages for AI accelerators, data center CPUs and networking silicon. The goal is to boost bandwidth, cut latency and keep power in check without relying only on smaller transistors.
TSMC 3DFabric in the bigger business picture
How advanced packaging orders from AI and data center customers feed back into earnings, capex and the valuation of Taiwan Semiconductor (TSMC).
The building blocks: CoWoS, InFO and SoIC
One pillar of 3DFabric is CoWoS, short for chip-on-wafer-on-substrate, which mounts logic dies and HBM on a silicon interposer before placing the assembly on an organic substrate. TSMC offers several CoWoS variants, including CoWoS-S with silicon interposers and CoWoS-R with organic redistribution layers.
InFO, or integrated fan-out, removes the traditional substrate and uses redistribution layers to spread signals from the chip to solder balls, reducing package thickness and improving electrical performance. This technology appears in mobile system-on-chip packages and some high-performance devices.
Vertical stacking with SoIC
At the 3D end, SoIC (System on Integrated Chips) allows TSMC to stack dies vertically using direct copper-to-copper bonding, without solder microbumps in between. This shortens interconnect length and can reduce power consumption for die-to-die communication.
SoIC comes in face-to-face and face-to-back configurations, enabling designers to place logic on logic or logic next to SRAM or other functions. TSMC markets SoIC together with CoWoS and InFO under the 3DFabric brand, promising a menu of stacking options rather than a single recipe.
Who uses 3DFabric today
TSMC does not name every customer, but industry analysts and device teardowns show that major GPU and AI accelerator vendors rely on CoWoS packaging to pair compute dies with HBM stacks for training and inference workloads. Network switch ASICs and high-performance CPUs also appear in CoWoS-based modules.
In the consumer space, InFO packages have appeared in smartphone application processors, where thin profiles and fine-pitch routing matter. 3DFabric's mix of options lets chip designers cross over between these markets as they add chiplet-based variants.
Why the CEO talks about packaging capacity
When TSMC CEO C.C. Wei stands in front of analysts, he now routinely highlights advanced packaging and 3D capacity alongside leading-edge nodes. The company has announced capacity expansions for CoWoS to respond to AI-related demand.
Wei frames 3DFabric as a strategic complement to core process technology, not just a backend side business. As customers push toward chiplet architectures, packaging becomes a lever for performance and time-to-market, which in turn shapes long-term order visibility.
Costs, lead times and design trade-offs
3DFabric comes with higher packaging costs and more complex design rules than traditional wire-bond or flip-chip solutions. Engineers must consider power delivery, thermal management and signal integrity in three dimensions rather than just across a single die.
Lead times can also be longer because advanced packaging capacity is more constrained than basic assembly lines, especially for CoWoS where interposers and substrates involve additional process steps. Customers often reserve capacity months in advance to synchronize with chip tape-outs and system launch windows.
Competition in advanced packaging
TSMC faces competition from other foundries and outsourced semiconductor assembly and test (OSAT) companies that offer their own 2.5D and 3D packaging portfolios. Some rivals focus on fan-out panel-level packaging or hybrid bonding to differentiate their roadmaps.
However, TSMC benefits from tight integration between its leading-edge process nodes and its in-house packaging lines, allowing co-optimization of design rules and manufacturing flows across front-end and back-end. That integration strengthens the pitch behind the 3DFabric label.
How 3DFabric fits into TSMC's roadmap
3DFabric ties into TSMC's broader roadmap that also includes N3 and N2 process nodes, specialty technologies and automotive-qualified lines. The company positions advanced packaging as a critical enabler for chiplets and heterogeneous integration over the next decade.
New generations of SoIC and CoWoS are planned with finer pitches and larger reticle-sized interposers to support bigger AI accelerators and more memory stacks per package. This roadmap supports customers that want to scale systems even when Moore's Law delivers smaller transistor gains.
Investor angle and stock context
For investors, 3DFabric matters because it links advanced node wafers to higher-value back-end services, improving revenue per wafer and creating additional bottlenecks that can support pricing power during demand upswings. AI-related orders in particular help fill both front-end and back-end capacity.
On the Taiwan Stock Exchange, the Taiwan Semiconductor (TSMC) share trades in New Taiwan dollars, with market participants closely following news on leading-edge nodes and advanced packaging capacity because both shape medium-term earnings expectations.
TSMC 3DFabric key facts
- Product: TSMC 3DFabric advanced packaging platform
- Manufacturer: Taiwan Semiconductor Manufacturing Company Limited
- Category: B2B/Pro line (advanced semiconductor packaging)
- Market launch: 3DFabric brand introduced in the early 2020s as an umbrella for existing and new packaging technologies
- MSRP / Price: Project-based pricing, typically quoted per wafer and per package for foundry customers
- Availability: Offered to qualified foundry customers globally, subject to capacity and design enablement
- Target group: Chip designers and system companies in AI, data centers, networking, mobile and high-performance computing
- Highlight / USP: Combines 2.5D and 3D chip stacking options such as CoWoS, InFO and SoIC under one integrated platform
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