AI-driven signoff, Cadence Cerebrus and Pegasus ECO turbocharge chip design

Cadence is pushing deeper into AI-assisted EDA with its Cerebrus Intelligent Chip Explorer and Pegasus ECO design-for-manufacturability platform, aiming to cut power, area and time-to-signoff for advanced-node chips in one integrated signoff flow.

Edited by ad hoc news New Releases & Launches Desk. Reviewed before publication on 06/16/2026 at 12:47 PM ET. Details in the imprint.

Cadence Design Systems is pushing AI-assisted chip design deeper into the signoff phase with its Cerebrus Intelligent Chip Explorer working in tandem with the Cadence Pegasus ECO platform, a design-for-manufacturability and signoff optimization solution that targets both power and area for advanced-node system-on-chips. According to Cadence, Pegasus ECO uses foundry-qualified engines and AI-driven exploration to reduce leakage power, dynamic power and die size while still meeting tight timing and physical verification constraints. Cadence’s official Cerebrus product page describes the broader AI platform as capable of exploring thousands of implementation options autonomously to optimize power, performance and area for complex SoCs.

How Pegasus ECO fits into Cadence’s AI-first signoff strategy

Within Cadence’s expanding digital design and signoff suite, Pegasus ECO sits alongside Pegasus Verification System as the piece focused on physical signoff optimization, including design rule checking (DRC), layout-versus-schematic (LVS) and layout finishing at advanced process nodes. The Pegasus ECO flow builds on traditional signoff capabilities by introducing automated engineering change order (ECO) optimization that can adjust placement, buffering and routing to fix last-minute timing or manufacturability issues while minimizing impact on power and area. In the context of Cadence’s AI initiatives, Cerebrus orchestrates upstream implementation choices, while Pegasus ECO provides a signoff-stage safety net where design teams can still squeeze out power and area savings without reopening the full place-and-route cycle, which is especially critical for 3 nm-class and upcoming 2 nm-class chips where each percent of leakage or area matters for cost and yield. Cadence highlights the Pegasus platform as its scalable signoff environment, compatible with large, multi-billion-transistor designs.

Cadence has been pairing these tools with foundry-specific enablement for leading-edge nodes, as illustrated by its expanded collaboration with Intel Foundry to co-optimize Intel’s 14A process technology using Cadence’s AI-driven EDA platforms and design IP. Industry reports on that partnership underscore that Cadence is working with Intel to deliver production-ready design kits and design technology co-optimization (DTCO) flows, which are intended to reduce design risk and accelerate customer tape-outs on the 14A node. This kind of co-optimization suggests that Pegasus ECO and the broader signoff stack are being tuned not only for generic design-rule compliance but also for node-specific variability, density rules and multi-patterning constraints, areas where automated ECO optimization backed by AI-guided exploration can save weeks of manual iteration. EE Times Asia’s report on the Cadence-Intel 14A partnership points to DTCO as a central theme, aligning process features and design methodologies.

For Cadence, Pegasus ECO and Cerebrus exemplify a broader pivot from point tools to integrated, AI-enhanced platforms that promise measurable reductions in time-to-signoff and engineering effort. The company has repeatedly framed its AI portfolio as targeting double-digit improvements in power, performance and area, along with shorter schedules and reduced need for manual tuning, which can translate into lower project risk and better economics for both fabless chip designers and foundry customers. As Cadence layers foundry partnerships on top of these platforms, the practical value of Pegasus ECO will hinge on how well its automated ECO optimizations track silicon results and how quickly new process-specific decks and flows reach customers for each new node generation.

Within Cadence’s product lineup, the Pegasus ECO flow complements the company’s digital implementation tools such as Innovus and Genus, and ties into its verification and IP offerings for end-to-end SoC development targeting mobile, data center, AI accelerator and automotive markets. For design teams facing aggressive power budgets and area targets, especially in AI infrastructure and high-performance computing, the ability to perform late-stage ECO optimization without derailing schedules can be a competitive advantage when tape-out windows are tight or when silicon re-spins would be prohibitively expensive. The increasing complexity of design rules at 3D packaging levels, including 2.5D and 3D IC configurations, adds further pressure on signoff tools to handle massive layouts efficiently, a demand that Cadence aims to address through the scalability of the Pegasus platform and its ability to distribute verification and ECO workloads across compute farms.

Cadence has also been vocal about aligning its AI and signoff roadmaps with sustainability and energy-efficiency goals in semiconductor manufacturing, positioning low-power design and optimized layouts as levers to reduce data center energy consumption and improve the carbon footprint of compute workloads. While those broader claims are harder to quantify on a per-tool basis, the combination of Cerebrus for exploration and Pegasus ECO for final optimization offers a concrete pathway for design teams to systematically minimize power and area, which in turn can allow smaller dies, better yields and potentially fewer wafers per product over time. In practice, engineering teams will judge Pegasus ECO by how many manual ECO iterations it can eliminate, how seamlessly it integrates with existing Cadence flows, and whether it keeps pace with the rapid cadence of new node introductions at partner foundries.

Cadence Design Systems positions its AI-driven EDA platforms, including Cerebrus and Pegasus ECO, as strategically important growth engines that support its long-term revenue mix in digital design, IP and system analysis, alongside its collaborations with leading foundries and hyperscale chip designers. Shares of Cadence Design Systems (US12541W1027) trade on the NASDAQ in USD; in mid-June 2026, the stock recently changed hands in the high-$380s per share, reflecting investor expectations for continued demand in advanced-node design software and AI-enabled EDA flows.

Cadence Pegasus ECO and Cerebrus in brief

• Product: Cadence Pegasus ECO (with Cerebrus Intelligent Chip Explorer)
• Manufacturer: Cadence Design Systems Inc.
• Category: New Release/Launch - AI-assisted EDA signoff platform
• Launch date: Pegasus ECO introduced as part of the Pegasus platform in recent tool generations; Cerebrus was first announced in 2021 and has since been expanded
• MSRP / Price: Not publicly listed; licensed to enterprise customers as part of Cadence’s digital design and signoff tool portfolio
• Availability: Offered directly by Cadence worldwide to semiconductor design houses and foundry customers as part of enterprise EDA contracts
• Target audience: Semiconductor design teams and foundry partners working on advanced-node SoCs and 3D ICs
• Key differentiator / USP: AI-assisted ECO optimization at signoff, tuned for advanced process nodes and integrated with Cadence’s broader digital implementation and verification suite

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